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| ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers. For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02. For CMOS in and PECL out with zero delay, use the ICS527-03. Features * * * * * * * * * * * * * * Packaged as 28-pin SSOP (150 mil body) Synchronizes fractional clocks rising edges CMOS in to PECL out PECL in to PECL out Pin selectable dividers Zero input to output skew User determines the output frequency - no software needed Slices frequency or period Input clock frequency of 1.5 MHz - 200 MHz Output clock frequencies up to 160 MHz Very low jitter Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Block Diagram R6:R0 7 PECLIN PECLIN Divide by 2 1 0 Reference Divider Phase Comparator, Charge Pump, and Loop Filter Divide by 2 1 0 Feedback Divider 2 VCO Output Divider 2 VDD RES 560 ohm VDD VDD 68 ohm PECLO 180 ohm VDD 68 ohm PECLO 180 ohm 7 F6:F0 GND 2 S1:S0 FBPECL FBPECL IRANGE MDS 527-04 D Integrated Circuit Systems, Inc. 1 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Pin Assignment R5 R6 IR A N G E S0 S1 VDD FBPECL FBPECL GND P E C L IN P E C L IN F0 F1 F2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R4 R3 R2 R1 R0 VDD PECLO PECLO GND RES F6 F5 F4 F3 Output Frequency and Output Divider Table S1 Pin 5 0 0 1 1 S0 Pin 4 0 1 0 1 Output Frequency (MHz) PECLO Output Pair 10 - 80 5 - 40 2.5 - 20 20 -160 IRANGE Setting Table IRANGE 0 1 Criteria if (FBPECL < 80 MHz) and (PECLIN < 80 MHz) if (FBPECL > 80 MHz) or (PECLIN > 80 MHz) 28-pin (150 mil) SSOP Pin Descriptions Pin Number 1-2 24 - 28 3 4-5 6, 23 7 8 9, 20 10 11 12 - 18 19 21 22 Pin Name R5, R6, R0-R4 IRANGE S0, S1 VDD FBPECL FBPECL GND PECLIN PECLIN F0-F6 RES PECLO PECLO Pin Type Input Input Input Power Input Input Power Input Input Input BIAS Output Output Pin Description Reference divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up. Set for proper frequency range of input clocks. See table above. Select pins for output frequency range. See table above. Internal pull-up. Connect to +3.3 V. PECL feedback input to PLL. PECL feedback input to PLL. Connect to ground PECL input clock. Complementary PECL input clock. Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up Resistor connection to VDD for setting level of PECL outputs. Complementary PECL output. PECL output. Rising edge aligns with PECLIN when connected directly to FBPECL. MDS 527-04 D Integrated Circuit Systems, Inc. 2 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer External Components Decoupling Capacitors The ICS527-04 requires two 0.01F decoupling capacitors to be connected between VDD and GND, one on each side of the chip. They must be connected close to the device to minimize lead inductance. The output levels can be adjusted for different output and load impedances. Refer to application note MAN09 for more information on the RES and resistor network values for the output clocks. Determining ICS527-04 Divider Settings The user has full control in setting the desired output clock over the range shown in the table on page 2. The user should connect the divider select input pins directly to ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board layout, so that the ICS527-04 automatically produces the correct clock when all components are soldered. It is also possible to connect the inputs to parallel I/O ports in order to switch frequencies. The configuration inputs: IRANGE, S1, S0, R6...0, F6...0 are compatible with CMOS or TTL levels. The output of the ICS527-04 can be determined by the following simple equation: FB Frequency = Input Frequency x ----------------------FDW + 2 RDW + 2 PECL Termination Networks The PECLO to FBPECL and PECLO to FBPECL connections should be made directly underneath the device, unless feedback is being routed through other devices. The resistor divider networks should be placed as close to the outputs as possible. Typical 50 termination is shown in the Block Diagram on page 1. For other termination schemes, see MAN09.pdf. Where: Reference Divider Word (RDW) = 0 to 127 Feedback Divider Word (FDW) = 0 to 127 FB Frequency is the same as the output frequency Additionally, the following operating ranges should be observed: Input Frequency 300kHz < -----------------------------------------RDW + 2 Eliminating the Delay Through Buffers or Other Components More complicated feedback schemes can be used, such as incorporating low skew, multiple output buffers in the feedback path. An example of this is given later in the datasheet. The fundamental property of the ICS527-04 is that it aligns rising edges on CLKIN and FBPECL at a ratio determined by the reference and feedback dividers. This means that any delay in the feedback path will cause the PECL output edge to lead PECLIN by the delay amount. So, by taking the PECL output from another device as the input to FBPECL, the delay through the other device can be eliminated. S1 and S0 should be selected depending on the output frequency. The table on page 2 gives the ranges. The dividers are expressed as integers. For example, if a 50 MHz output on CLK1 is desired from a 40 MHz input, the reference divider word (RDW) should be 2 and the feedback divider word (FDW) should be 3 which gives the required 5/4 multiplication. If multiple choices of dividers are available, then the lowest numbers should be used. In this example, the output divide (OD) should be selected to be 2. Then R6:R0 is 0000010, F6:F0 is 0000011 and S1:S0 is 00. If you need assistance determining the optimum divider settings, please send an e-mail to ics-mk@icst.com with the desired input clock and the desired output frequency. Setting the Clock Slicer Use IRANGE to select the input frequency range. If either the PECLIN or FBPECL pair frequencies are greater than (or equal to) 80 MHz, connect IRANGE to VDD, or let it float. If both frequencies are less than 80 MHz, connect IRANGE to ground. Choose S1 and S0 from the table on page 2, depending on the output frequency. Finally, the divider settings should be selected. Following is a description of how the dividers should be set. MDS 527-04 D Integrated Circuit Systems, Inc. 3 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Typical Example The following connection diagram shows the implementation of the example from the previous section. This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will produce the waveforms shown on the bottom of the example. VDD R5 R6 IRANGE S0 0.01 F R4 R3 R2 R1 R0 VDD PECL PECL GND RES F6 F5 F4 F3 560 180 0.01 F S1 VDD FBPECL FBPECL GND VDD 50 MHz 40 MHz 40 MHz PECLIN PECLIN F0 F1 F2 PECL output resistor network (50 ohm) is not shown, but is identical to PECL 40 MHz (PECLIN shown) 50 MHz PECL 50 MHz PECL MDS 527-04 D Integrated Circuit Systems, Inc. 4 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Multiple Output Example In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL buffer with low pin to pin skew. VDD R5 R6 IRANGE S0 0.01 F R4 R3 R2 R1 R0 VDD ICS527-04 0.01 F RN OE NC VDD VDD S1 VDD FBPECL Q0 ICS554-01A Q3 RN PECLO PECLO GND RES F6 F5 F4 F3 RN RN RN 0.01 F RN Q0 Q3 RN 0.01 F 50 MHz FBPECL GND Q1 Q2 RN 125 MHz 125 MHz PECLIN PECLIN F0 F1 F2 560 RN Q1 Q2 RN GND IN GND IN The layout design above produces the waveforms shown below. 125 MHz, PECLIN 50 MHz, PECLO (Complementary outputs are not shown) Using the equation for selecting dividers gives: 50 MHz = 125 MHz * (FDW + 2) (RDW + 2) If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and FBPECL pins. In this example, the resistor network needed for each PECLO output is represented by the RN boxes. MDS 527-04 D Integrated Circuit Systems, Inc. 5 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No via's should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) PECL termination networks should be located as close to the outputs as possible. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through other Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS527-04. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature 7V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. 0 +3.15 Typ. +3.3 Max. +70 +3.45 Units C V MDS 527-04 D Integrated Circuit Systems, Inc. 6 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Operating Voltage Input High Voltage Input Low Voltage Peak to Peak Input Voltage Common Mode Range Output High Voltage Output Low Voltage Operating Supply Current Input Capacitance On-chip pull-up resistor Symbol VDD VIH VIL Conditions Min. 3.15 2 Typ. 3.3 Max. 3.45 Units V V 0.8 Pins 7, 8, 10, 11 Pins 7, 8, 10, 11 0.3 VDD-1.4 2.4 0.4 8 4 configuration inputs 270 1 VDD-0.6 V V V V V mA pF k VOH VOL IDD CIN RPU IOH = -12 mA IOL = 12 mA 15 MHz in, 60 MHz out, no load AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C Parameter Input Frequency Output Frequency, CLK1 Output Duty Cycle Absolute Clock Period Jitter One sigma Clock Period Jitter Input to output skew Device to device skew Symbol FIN FOUT tOD tja tjs tIO tpi Conditions 0 to +70C Min. 1.5 4 45 Typ. Max. 200 160 Units MHz MHz % ps ps 50 90 40 55 Deviation from mean PECLIN to PECLO, Note 1 Common CLKIN, measured at FBPECL -250 250 500 ps ps Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 100 80 67 60 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case MDS 527-04 D Integrated Circuit Systems, Inc. 7 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Marking Diagram 28 15 ICS $$###-### YYWW ICS527R-04 14 1 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. MDS 527-04 D Integrated Circuit Systems, Inc. 8 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body, 0.025 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153 28 Millimeters Symbol Min Max Inches Min Max E1 INDEX AREA E 12 D A A1 A2 b C D E E1 e L aaa 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 9.80 10.00 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0 8 -0.10 .053 .069 .0040 .010 -.059 .008 .012 .007 .010 .386 .394 .228 .244 .150 .157 0.025 Basic .016 .050 0 8 -0.004 A 2 A 1 A c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS527R-04 ICS527R-04T Marking ICS527R-04 ICS527R-04 Shipping packaging Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP Temperature 0 to +70C 0 to +70C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments MDS 527-04 D Integrated Circuit Systems, Inc. 9 525 Race Street, San Jose, CA 95126 Revision 122804 tel (408) 297-1201 www.icst.com |
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